J. Circuits Syst. Comput.

2018, 27, 1850206

A 16.4 nW, sub-1V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8 V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down V-be, respectively, to improve the process insensitivity. This work is fabricated in 0.18 mu m CMOS process with a total area of 0.0033 mm(2). Measured results show that it works properly for supply voltage from 0.8 V to 2 V. The reference voltage is 467.2 mV with standard deviation (sigma) being 12.2 mV and measured TC at best is 38.7 ppm/degrees C ranging from -40 degrees C to 60 degrees C. The total power consumption is 16.4 nW under the minimum supply voltage at 27 degrees C.